1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a liquid crystal display (LCD) and a method for fabricating the same.
2. Discussion of the Related Art
In a conventional LCD, an amorphous silicon (a--Si) has been a choice of material for a thin film transistor (TFT) to fabricate an LCD. However, a polysilicon becomes a substitute for the amorphous silicon for the TFT because the polysilicon has a carrier (electron or hole) mobility that is higher than that of the amorphous silicon. Additionally, the polysilicon TFT has an advantage of forming the driving circuit on the LCD panel during the fabrication of pixels. Also, a complimentary metal-oxide-semiconductor (CMOS) TFT is easily realized by the polycrystaline silicon.
Accordingly, in fabricating the polysilicon TFT-LCD, since most of the drive circuit is formed with the polysilicon TFT, driver ICs(Intergrated Circuits) do not need to be bonded to the LCD panel. Thus, fabricating the drive circuit and the pixel on the LCD panel simultaneously becomes a feasible process. Furthermore, the polysilicon TFT can be fabricated on a larger glass substrate at low temperature below 500.degree. C. due to a recently developed crystallization technique using a eximer laser. As a result, the polysilicon TFT can be formed at similar fabrication temperature with the amorphous silicon TFT.
As described above, the polysilicon TFT-LCD employs a structure where the drive circuit portion and pixel portion are formed on the same glass substrate. The TFT at the drive circuit can be switched at high speed due to the high carrier mobility of the polysilicon TFT. However, since the TFT for switching the pixel has a high drain current at off-state, a TFT having a lightly doped drain (LDD), offset or dual gate structure has been suggested in order to reduce the off-current to a desirable level at the pixel portion.
FIG. 1 is an equivalent circuit diagram of a conventional LCD in which a drive circuit is formed on an insulating substrate. As shown in FIG. 1, a plurality of signal lines 5 and scanning lines 4 intersect with each other and are arranged in a matrix form at the pixel portion on a transparent substrate. A pixel electrode 6 and a TFT 9 for driving the pixel portion are formed at the intersection. A common electrode 8 for displaying pictures is formed on the other transparent substrate. Also, a storage capacitor 7 is formed to be electrically parallel with the pixel electrode 6 and the common electrode 8.
A gate drive circuit 1 and a data drive circuit 2 are formed at the periphery of the pixel portion. These circuits apply a desirable signal to the pixel portion. The gate drive circuit 1 and the data drive circuit 2 are simultaneously formed on the same insulating substrate.
FIG. 2A is a plan view of the pixel portion of a conventional LCD, and FIG. 2B is a cross-sectional view taken along line I--I' of FIG. 2A. A signal line 40 and a scanning line 50 intersect or cross each other on an insulating substrate 1000, and a source region 11S at the TFT is connected to the signal line 40. A drain region 11D is connected to a pixel electrode 15. The drain region 11D and a first storage capacitor electrode 17 are formed as one layer. A gate electrode 14 connected to the scanning line 50 is formed on a gate insulating layer 100. A second storage capacitor electrode 18 forms a storage capacitor together with the first storage capacitor electrode 17. A gate insulating layer 100 is formed between the first and second capacitor electrodes. The second storage capacitor electrode 18 and the gate electrode 14 are formed of a same material and the same layer.
Source and drain regions 11S and 11D of the TFT are heavily doped regions with N-type or P-type ions. An LDD region 12 is formed adjacent to the heavily doped region so as to reduce the leakage current when the TFT is at the off-state. Reference numeral 200 designates an interlevel insulating layer, and reference numeral 300 designates a passivation layer.
FIGS. 3A to 3H are cross-sectional views showing process steps of fabricating the conventional LCD. In these drawings, the left portion shows the TFT for the pixel and the right portion shows the CMOS-TFT for the drive circuit portion.
As shown in FIG. 3A, a polysilicon is formed on a substrate 1000 and patterned to form semiconductor layers 10', 20n' and 20p' on the pixel and drive circuit portions, respectively. The semiconductor layer 10' corresponds to the pixel portion, and the semiconductor layers 20n' and 20p' are for the drive circuit portion. The semiconductor layers 20n' and 20p' are used to form an N-type TFT and P-type TFT, respectively.
As shown in FIG. 3B, a predetermined type of impurity is selectively implanted into the semiconductor layer 10' (which will be an active layer 10 at the pixel portion) to form a first storage capacitor electrode 17. The type of impurity to be doped is the same as that of the source and drain regions which are formed as follows. For example, for a pixel TFT of an N-type, N-type impurity ions are selectively implanted only into the first storage capacitor electrode region using a photoresist 61 as a mask. Thereafter, the photoresist 61 is removed, and the first storage capacitor electrode region is irradiated by a laser or heated by a conventional method in order to activate the impurity ions implanted in the previous step.
As shown in FIG. 3C, an insulating material including silicon oxide or silicon nitride is deposited on the substrate 1000 including the first storage capacitor electrode 17 to form a gate insulating layer 100. Successively, a metal such as Al, Al alloy, Mo, or Cr is deposited on the gate insulating layer 100 and patterned through photolithography to form a gate electrode 14 for the pixel TFT and gate electrodes 24n and 24p for the drive circuit TFT on the gate insulating layer 100. In this process, a second storage capacitor electrode 18 is also formed at the pixel portion. That is, the gate electrode 14 and the second storage capacitor electrode 18 are formed using the same material.
As shown in FIG. 3D, N-type impurities are doped lightly into the exposed surface over the substrate to form the LDD TFT. In the process of implanting the impurities, the gate electrodes 14, 24n, and 24p act as masks to block the ions. Thus, an n.sup.- layer 12', 21' and 22' and channel layers 10, 20n, and 20p are formed in semiconductor layers 10', 20n', and 20p' (shown in FIG. 3A), respectively.
Alternatively, when n.sup.- impurities are doped with a low ion implantation energy, an insulating layer including a silicon oxide layer or a silicon nitride layer and a metal layer such as Al, Al alloy, Mo, or Cr are sequentially formed on the substrate. Then, the insulating layer and the metal layer are patterned simultaneously. As a result, the gate insulating layer 100 and the gate electrodes 14, 24n, and 24p are formed in the same patterning process, and a portion of the semiconductor layers 10', 20n', and 20p' are exposed as shown in FIG. 3X. Thereafter, N-type impurities are doped with a low ion implantation energy into the exposed surface over the substrate. Accordingly, the exposed portions of the semiconductor layers 12', 21', and 22', which are not blocked by the gate electrodes, is lightly doped with impurities and becomes the n.sup.- layer. Furthermore, the channel layers 10, 20n, and 20p are formed at portions of the semiconductor layer below the gate electrodes 14, 24n, and 24p. Thus, in the alternative embodiment, the impurities are directly implanted into the semiconductor layer unlike the process shown in FIG. 3D.
As shown in FIG. 3E, a photoresist is coated on the exposed surface over the substrate and patterned to form a photoresist pattern 62 to cover a P-type TFT region at the drive circuit and the gate electrode 14 and a portion of the semiconductor layer at the pixel TFT. Then, N-type impurities are heavily doped using the photoresist pattern as a mask. In this process, since the photoresist pattern 62 is formed on the pixel portion to cover the gate electrode 14 and a portion of the semiconductor layer, the impurities are selectively doped into a portion of the n.sup.- layer. Accordingly, source 11S and drain 11D are formed to have a heavily doped n.sup.+ layer and a lightly doped n.sup.- layer 12 in the semiconductor layer at the pixel portion to complete an LDD structure.
On the other hand, at the drive circuit portion, the P-type TFT region is covered with photoresist pattern 62 and the n.sup.+ doping is carried out on a portion of the semiconductor layer at the N-type TFT region to form source and drain regions 21S and 21D and an N-type channel 20n. Accordingly, the TFT having an LDD structure with the n.sup.+ and n.sup.- layers is formed at the pixel portion, while the N-type TFT having the n.sup.+ layer and the P-type TFT having the p.sup.+ layer are formed at the drive circuit portion.
As shown in FIG. 3F, after the photoresist pattern 62 is removed, another photoresist is coated on the substrate and patterned to form a photoresist pattern 63. The photoresist pattern 63 covers a large portion and exposes the P-type TFT region at the drive circuit portion. Then, P-type impurities are heavily doped into the substrate using photoresist pattern 63 as a mask. As a result, source and drain regions 23S and 23D are formed having a p.sup.+ layer, and a P-type channel region 20p is formed in a portion of the semiconductor layer at the P-type TFT region in the drive circuit portion.
The above-mentioned impurity doping method is called a counter doping. In the n.sup.- doping (FIG. 3D), the concentration of the ion doped into the semiconductor is approximately 10.sup.16 .about.10.sup.18 /cm.sup.3 for n.sup.31 doping and about 10.sup.10 .about.10.sup.21 /cm.sup.3 for p.sup.- doping. Accordingly, the n.sup.- layer is converted to p.sup.+ layer by the p.sup.+ doping.
As shown in FIG. 3G, after the remaining photoresist pattern 63 is removed, an insulating layer, for example, a silicon nitride layer, is formed on the exposed surface over the substrate 1000 to form an inter-layer insulating layer 200. Then, the inter-layer insulating layer 200 is patterned to form contact holes over a source region 11S at the pixel portion and source regions 21S and 23S and drain regions 21D and 23D at the drive circuit portion. A metal such as Al is deposited on the substrate and patterned to form a signal line 40 connected to the source region 11S at the pixel portion. A metal line 25 for connecting the source and drain regions at the drive circuit is formed in order to form a CMOS-TFT with the N-type and P-type TFTs at the drive circuit portion. Accordingly, the LDD structured TFT and the CMOS-TFT are formed at the pixel portion and the drive circuit portion, respectively.
As shown in FIG. 3H, an insulating layer is formed on the exposed surface over the substrate to form a passivation layer 300. Thereafter, a portion of the gate insulating layer 100, the inter-layer insulating layer 200, and the passivation layer 300 on a drain region 11D are selectively etched through photolithography to form a contact hole over the drain region 11D. Then, an Indium Tin Oxide (ITO) is deposited on the exposed surface over the substrate and patterned to form a pixel electrode 15.
After the aforementioned process of fabricating a bottom substrate for the LCD, a top plate including a color filter is fabricated through a separate process. Then, after the two plates are bonded to each other, liquid crystal is injected between the two plates to complete the TFT-LCD.
The above-described conventional TFT-LCD employs a CMOS-TFT as a drive circuit TFT for a better circuit performance. Also, the storage capacitor is formed on the pixel portion using the gate insulating layer formed between the active region and the gate electrode to improve the picture quality. Thus, the conventional method for fabricating the TFT-LCD requires at least nine steps of the photoresist and mask alignment to fabricate the TFT substrate.
As a result, since the number of process steps is increased, the productivity and the yield are decreased dramatically. Moreover, with regard to the switching operation at the pixel TFT, leakage current of the polysilicon TFT is large at an off-region. Thus, the LDD structure must be formed using additional photoresist steps. This makes the fabricating process very complicated, and drives up the production cost.